1. Field of the Invention
The present invention generally relates to data processing devices, and particularly relates to a signal processing accelerator which is incorporated into a personal computer to effect high-speed processing of multi-media data or the like.
2. Description of the Related Art
Recent expansion in the number of application fields of data processing has resulted in an increasing demand for a device which can process a vast amount of data such as image and audio data at high speed. In particular, multi-media equipment is required to process image and audio data or the like at high speed in line with the display speed of moving pictures.
Multi-media equipment for high-speed data processing generally has a system configuration which incorporates a number of pieces of dedicated hardware for respective signal processing. When high-speed data processing is achieved through dedicated hardware, however, such a system has drawbacks in costs and lack of expandability and upgradability of the equipment. That is, costs are incurred with respect to design, development, and manufacture of dedicated hardware for respective signal processing, so that a resulting system incorporating the dedicated hardware becomes expensive. Further, dedicated hardware is designed for specific data processing, and, thus, is limited in use thereof because only limited types of processing is executable by such hardware. A problem of lack of expandability and upgradability thus arises when there is a need to apply the hardware to a new application field.
Recent enhancement in speed and performance of general-purpose processors has made it possible to use general-purpose processors for high-speed data processing. When compared with systems of dedicated hardware described above, systems employing such general-purpose processors are characterized in that software is used for achieving various signal processing functions. Such software-based systems for achieving various signal processing functions have advantages in that they are implemented at relatively low cost and have superior functional expandability when compared to the dedicated-hardware systems.
However, software-based systems employing general-purpose processors have disadvantages as follows.
First, since general-purpose processors in these software-bases systems are required to run operating systems (OSs), the general-purpose processors cannot be used exclusively for signal processing. Namely, since OS tasks need to be executed during the signal processing, it is difficult to sufficiently step up the signal processing speed. This poses a problem, especially, when real-time processing is required.
Second, general-purpose processors are designed for handling general data operations, but are not suitable for signal processing. Because of this, general-purpose processors cannot exhibit desirable performance in a field such as image processing where parallel data processing is preferred.
Third, when data transfer is conducted via a bus between a general-purpose processor, memories, I/O ports, etc., an increase in bus access may result in access collisions between data transfer for the signal processing and data transfer for other processes such as OS tasks, thereby reducing the speed of data transfer. For example, when data is first transferred from an I/O port to a memory, then transferred many times between the memory and a general-purpose processor to carry out signal processing, and finally transferred from the memory to the I/O port, the frequency of bus access is quite high. In such a case, a decrease in data-transfer speed due to access collisions cannot be avoided.
The software-based signal processing systems employing general-purpose processors also have a problem in that a sufficient data processing speed cannot be achieved because of the three reasons identified above. This problem becomes particularly conspicuous when a plurality of signal processing operations need to be simultaneously carried out as required in multi-media signal processing.
On the other hand, a system configuration which incorporates DSPs (digital signal processors) or the like specifically designed for signal processing can achieve processing of image and audio data at such a speed as to meet various requirements. Further, so-called multi-media-extended-instruction-set processors (e.g., P55C of the Intel corporation) are now available, and these processors are equipped with signal processing functions as extended instructions in addition to an original set of instructions.
Such a system, however, incurs additional costs for design, development, and manufacture of dedicated hardware portions for signal processing. Also, bus collisions at a time of data transfer place a cap on the data processing speed as described above. Accordingly, this system cannot exhibit a desirable performance because of bus-access conflict between a plurality of signal processing operations particularly when such a plurality of signal processing operations need to be simultaneously carried out as in multi-media signal processing.
Accordingly, there is a need for an architecture of a signal processing accelerator which is incorporated into a personal computer or the like and can achieve a sufficient signal processing speed at a relatively low cost.
Accordingly, it is a general object of the present invention to provide a signal processing accelerator having an architecture which can satisfy the need described above.
It is another and more specific object of the present invention to provide a signal processing accelerator having an architecture which is incorporated into a personal computer or the like and can achieve a sufficient signal processing speed at a relatively low cost.
In order to achieve the aforementioned objects according to the present invention, a device for signal processing includes a plurality of information processing units and communication links connected between the information processing units. Each of the information processing units includes a signal processing unit for processing data, a communication control unit for communicating with other information processing units via the communication links, and a storage unit for storing data and programs executed by the signal processing unit. The storage unit is used for data exchange between each of the information processing units and an external bus.
In the device described above, the plurality of information processing units can communicate with each other without using the external bus, so that high-speed signal processing is achieved by avoiding a reduction in data processing speed caused by bus conflict. Further, a plurality of processes such as image processing and audio processing can be allocated to different information processing units, so that this device is suited to multi-media signal processing which requires processing of a plurality of different signals.
According to one aspect of the present invention, the storage unit includes a memory for storing the data and the programs and a memory control unit for controlling the memory such that the memory is accessible from the external bus when the data exchange is conducted.
Accordingly, if the signal processing unit, the communication control unit, and the storage unit are implemented on a single chip as an integrated circuit, the device can be incorporated in a personal computer or the like in the same manner as conventional memory devices are incorporated. Because of this, costs for incorporating the above device can be included in the costs of the memory devices, and the device inserted into the memory devices can be utilized by using software. In this manner, costs of hardware extension can be reduced while providing a system having a functional expandability.
According to another aspect of the present invention, the memory control unit includes a key-data storage unit for storing key information, and controls the memory such that the memory is accessible from the external bus only when data matching the key information is provided from the external bus.
In the device described above, the memory of the storage unit is generally conditioned so as not to be accessible as a memory from the external bus, thereby preventing the operation system of a host processor from taking control of the memory for use as an OS memory space. Only when the keys are unlocked, will data exchange between the host processor and the information processing units become possible.
According to yet another aspect of the present invention, when a process is comprised of procedures which can be simultaneously carried out in parallel, the information processing units are operated in parallel, thereby achieving high-speed data processing.
According to yet another aspect of the present invention, when a process is comprised of procedures among which a given procedure requires results of another procedure and any procedure needs to be repeated, the information processing units are operated in a pipe-line manner such that all procedures are carried out at the same time by respective information processing units, thereby achieving high-speed data processing.
According to still another aspect of the present invention, when a host processor (CPU) generates an interruption upon fetching and decoding a particular instruction, the information processing units can serve as a virtual machine by executing this instruction on behalf of the host processor. This configuration allows the system to run a program as if the host processor executed such an instruction.
According to further aspect of the present invention, a first resource-management program and a second resource-management program are provided in an application interface layer and a device-driver layer, respectively, and control process allocation and data connection as well as hardware of the information processing units. Because of this configuration, data to be processed does not have to be brought all the way up to the uppermost application layer where user programs and application programs reside, so that efficient processing is carried out with regard to data transfer.
Other objects and further features of the present invention will be apparent from the following detailed description when read in conjunction with the accompanying drawings.